1. Field of the Invention
This invention relates to improvements in EEPROM devices, and methods for making the same, and more particularly to improvements in the layout and construction of the floating gate of an EEPROM cell with respect to the tunnel region of the EEPROM cell, and methods for making the same; and still more particularly to improvements in a tunnel diode for conducting charge to and removing charge from a floating gate of an EEPROM device, and method for constructing the same.
2. Relevant Background
As advances are made in technologies related to electrically erasable read-only memory (EEPROM) devices, EEPROM devices are being introduced into many semiconductor processes, such as CMOS, BiCMOS, linearBiCMOS(trademark), and other advanced semiconductor processes. When EEPROM cells are produced for any process, factors contributing to improving the ability to manufacture such EEPROM devices, and the potential impact of such factors on reliability of the final devices, are of key concern.
Many EEPROM designs rely upon an associated tunnel diode to control the placement and removal of a charge onto and from the floating gate of the device, which controls the apparent threshold voltage of an associated MOS transistor. The charge on the floating gate is related to the charge that has passed through the tunnel diode. The tunnel diode typically is constructed with a doped tunnel diode region contained in the semiconductor substrate in which the EEPROM device is formed. The tunnel diode region is separated from the floating gate by a thin oxide layer, sometimes called the xe2x80x9ctunnel oxide.xe2x80x9d Among the many considerations that affect the design and construction of the tunnel diode region, the thickness and quality of the tunnel oxide are of basic importance. In previous EEPROM devices, the tunnel oxide generally has a thickness of about 100 xc3x85, and the quality of tunnel oxide impacts the reliability and performance of the final EEPROM cell.
Although the floating gate must overlie the tunnel region for the tunnel read and write mechanisms properly to operate, in the past, the typical layout of an EEPROM cell provided for the extents of the floating gate layer to intersect the extents of the tunnel diode region. Consequently, the floating gate only partially, or just, covered the tunnel diode region, but did not fully encompass it. Thus, the exposed portions of the tunnel region and the portions of the tunnel region at or immediately below the margins of the floating gate were susceptible to overetching. This was especially true during the floating gate etch steps or in subsequent semiconductor manufacturing processes. Such overetching, of course, may result in degraded EEPROM cell reliability.
Also in the past, in the formation of a tunnel diode in association with a MOS transistor, a first portion of a gate oxidation was performed to provide an initial oxide thickness over the tunnel diode region and its peripheral areas. Thicker field oxide may also have been concurrently formed over more highly doped regions of the substrate at which field adjust implants may have been made. The oxide directly over the tunnel region was then stripped to expose the substrate, and a dopant of appropriate type and conductivity to provide the desired tunnel region was introduced or implanted into the substrate. The exposed substrate area was then again oxidized to produce the proper tunnel oxide thickness, about 100 xc3x85. The surrounding oxide was also concurrently thickened, for example to a final thickness of about 200 xc3x85to 500 xc3x85.
After the tunnel region and oxidation had been completed, a polycrystalline silicon (polysilicon) floating gate was deposited, patterned, and etched. As mentioned, the floating gate was formed entirely within the tunnel oxide region, although the tunnel region implant typically extended to beneath the thicker peripheral gate oxide. This process may be performed in conjunction with the formation of a control gate in a dual polysilicon EEPROM cell, or independently in a single or dual polysilicon EEPROM cell.
In any event, a point exists in the process at which an etch is required to etch the floating gate, desirably which will stop on the underlying thin tunnel oxide. However, during such etching steps, stopping the etch exactly at the tunnel oxide level has been difficult to perform, and generally some overetch occured. The overetch may remove some of the tunnel oxide under the floating gate at its edges. Sometimes, the overetch extended completely through the tunnel oxide beyond the margins of the floating gate and into the tunnel region in the substrate. Such overetch is problematic, since although with future oxidations the overetched regions will regrow the removed oxide, the quality of the regrown oxide could be degraded. This may result in altered performance or reliability. In some case, if the overetch was severe, the reliability of the final EEPROM cell was compromised, and the ability to perform and repeat the process is questionable.
An additional concern is that some contaminants, such as etch residues, may be present in the areas near the tunnel region. These contaminants could affect the regrowth of the oxide, or simply by being present, degrade the reliability of the EEPROM cell. Also, these exposed regions may also be exposed to other etch processes later in the process. This increases the possibility of further silicon etch. This suggests that this approach is not ideal with respect to its ability to be successfully performed.
Considering the above, therefore, it is an object of the invention to provide an improved EEPROM device and method for making the same.
It is another object of the invention to provide an improved EEPROM structure and method for making the same that results in a device, which has increased reliability with respect to data retention and write/erase endurance, compared with EEPROM cells in which the floating gate does not completely overlap the tunnel region.
It is another object of the invention to provide an improved EEPROM structure and method for making the same that results in a device that has relaxed manufacturing requirements, without affecting the performance of the device.
It is yet another object of the invention to provide an improved tunnel diode construction for use with an EEPROM of the type in which a tunnel diode is employed to charge and discharge a floating gate in the EEPROM, and method for making the tunnel diode.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the accompanying drawings and appended claims.
This invention provides a layout technique by which a floating gate of an EEPROM cell can be constructed to overlie completely the tunnel diode region, thereby eliminating an exposed region of tunnel oxide. The invention enables a more manufacturable and repeatable floating gate etch, and eliminates the potential for subsequent processing steps to affect the tunnel diode area. Besides these manufacturability issues, the invention positively influences the reliability of the final EEPROM cell.
According to a broad aspect of the invention, a floating gate design is presented for use in an EEPROM cell structure constructed in a semiconductor substrate of first conductivity type. In the floating gate design, a first doped region of second conductivity type has a first doping concentration to provide a tank at a surface of the substrate. A second doped region is provided in the tank at the surface of the substrate to provide a tunnel region. The second doped region is of second conductivity type and has a second doping concentration more than the first doping concentration. A layer of insulation is provided over the surface of the substrate, having a first thickness to provide a tunnel region over at least part of the doped region, and a second, larger, thickness elsewhere. A conducting floating gate is provided above the second doped region and at least part of the first doped region on the layer of insulation. The floating gate extends laterally beyond the lateral boundaries of the second doped region in every direction, and has at least one side within lateral boundaries of the tank, extending over the thicker portion of the layer of insulation.
According to another broad aspect of the invention, a method is presented for making a floating gate in an EEPROM cell construction process. The method includes forming a first doped region in a semiconductor substrate of first conductivity type. The first doped region is of a second conductivity type, and has a first doping concentration to provide a tank at a surface of the substrate. A second doped region of second conductivity type is formed with a second doping concentration more than the first doping concentration to provide a tunnel region in the tank at the surface of the substrate. A layer of insulation is formed over the surface of the substrate with a first thickness to provide a tunnel region over at least part of the second doped region and a larger, thickness elsewhere. A floating gate that can hold an electrical charge, such an polysilicon, is provided above the second doped region and at least part of the first doped region on the layer of insulation. The floating gate extends laterally beyond lateral boundaries of the second doped region in every direction, and has at least one side within lateral boundaries of the tank, extending over the thicker portion of the layer of insulation.
According to another broad aspect of the invention, an EEPROM cell is provided. The EEPROM cell has a tank region in a semiconductor substrate, the tank region being of different conductivity from that of the substrate. A tunnel region in the tank region is of the same conductivity type as the tank. A layer of tunnel insulation, such as a silicon oxide, overlies the tank and tunnel region. The layer of insulation has a first thickness, such as about 100 xc3x85, over at least part of the tunnel region, and a thickness, such as about 200 xc3x85 or more, larger than the first thickness elsewhere. A floating gate of conducting material, such as polysilicon, is located above the tunnel region, the floating gate being sized to extend beyond the channel in all directions. The floating gate completely overlies the insulation of first thickness, and at least partially overlies the insulation of greater thickness. Transistor source, drain, and channel regions of the different conductivity type are formed in the substrate, with part of the floating gate lying over the channel. A layer of control gate insulation is formed over at least a portion of the floating gate and channel, and a control gate is formed over the channel and control gate insulation.
According to yet another broad aspect of the invention, a method is presented for making an EEPROM cell. The method includes forming a tank in a semiconductor substrate of different conductivity from the substrate. A tunnel region of the same conductivity type as the tank is formed in the tank. A layer of insulation is formed over the tank and tunnel region. The layer of insulation has a first thickness over at least part of the tunnel region, and a thickness larger than the first thickness elsewhere. For example, the layer of insulation may be a layer of silicon oxide of thickness of about 100 xc3x85 over the tunnel region, and about 200 xc3x85 or more elsewhere. A floating gate of a conductive material such as polysilicon is formed above the tunnel region, sized to extend beyond the tunnel region in all directions. Transistor source, drain, and channel regions are formed in the substrate with part of the floating gate overlying the channel.